Split Parallel Semibridge Switching Cells for Full-Power-Range Efficiency Improvement

This article proposes a positively coupled inductor (PCI) based paralleling scheme for basic semibridge switching cells, which are formed by power MOSFETs and diodes. Both the cells inductors split into two parallel parts, thus, small differential mode (DM) inductance is between midpoints of cells. A time-delay-based modulation strategy applied to generate controllable circulating current, enables all active switches achieve zero-current (ZCS) or zero-voltage switching, diodes ZCS turn-off. Accordingly, loss reverse-recovery can be significantly reduced. The operating principle proposed characterized complementary operation modes: desynchronized with soft-switching (lower loss) synchronized lower conduction loss. Compared conventional schemes, this solution features zero auxiliary switches, constant frequency, improved full-power-range efficiency enabled dual modes. Furthermore, design guidelines PCI presented where novel winding arrangement verified obtain DM inductance. principles advantages structure comprehensively validated on both buck boost dc-dc converters Si/SiC